---------------------------------------------------------------------------------------------------
--
-- Title       : pfsm2
-- Design      : PFSM1
-- Author      : Sasha
-- Company     : Nemchenko
--
---------------------------------------------------------------------------------------------------
--
-- File        : vhdl.vhd
-- Generated   : Sun Jan  4 19:40:42 2004
-- From        : interface description file
-- By          : Itf2Vhdl ver. 1.20
--
---------------------------------------------------------------------------------------------------
--
-- Description : 
--
---------------------------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.all;



entity PFSM_vhdl is
     port(
        CLK : in STD_LOGIC;
        Reset : in STD_LOGIC;
        X : in STD_LOGIC_VECTOR(1 to 5);
        Y : out STD_LOGIC_VECTOR(1 to 13)
         );
end PFSM_vhdl;

architecture behavioral of PFSM_vhdl is

type StateType1 is (a1, a14, e1, b1, a13);
type StateType2 is (b2, a2, a3, e2);
type StateType3 is (b3, e3);
type StateType4 is (b4, a4, a5, e4);
type StateType5 is (b5, a6, a7, e5);
type StateType6 is (b6, a8, a9, a10, a11, a12, e6);

signal State1, NextState1: StateType1;
signal State2, NextState2: StateType2;
signal State3, NextState3: StateType3;
signal State4, NextState4: StateType4;
signal State5, NextState5: StateType5;
signal State6, NextState6: StateType6;

signal sa1, sa2, sa3, sa4, sa5, sa6, sa7, sa8, sa9, sa10, sa11, sa12, sa13, sa14, 
       sb1, sb2, sb3, sb4, sb5, sb6,
       se1, se2, se3, se4, se5, se6: BOOLEAN;
        
signal f1b, f1e, f246c, f3e: BOOLEAN;

begin

-- Boolean

    sa1 <= true when State1 = a1 else false;
    sa2 <= true when State2 = a2 else false;
    sa3 <= true when State2 = a3 else false;
    sa4 <= true when State4 = a4 else false;
    sa5 <= true when State4 = a5 else false;
    sa6 <= true when State5 = a6 else false;
    sa7 <= true when State5 = a7 else false;
    sa8 <= true when State6 = a8 else false;
    sa9 <= true when State6 = a9 else false;
    sa10 <= true when State6 = a10 else false;
    sa11 <= true when State6 = a11 else false;
    sa12 <= true when State6 = a12 else false;
    sa13 <= true when State1 = a13 else false;
    sa14 <= true when State1 = a14 else false;
    sb1 <= true when State1 = b1 else false;
    sb2 <= true when State2 = b2 else false;
    sb3 <= true when State3 = b3 else false;
    sb4 <= true when State4 = b4 else false;
    sb5 <= true when State5 = b5 else false;
    sb6 <= true when State6 = b6 else false;
    se1 <= true when State1 = e1 else false;
    se2 <= true when State2 = e2 else false;
    se3 <= true when State3 = e3 else false;
    se4 <= true when State4 = e4 else false;
    se5 <= true when State5 = e5 else false;
    se6 <= true when State6 = e6 else false;
       
-- Special functions

    f1b <= (sa3 OR se2) AND (sa5 OR se4) AND (sa7 OR (sa6 AND x(3) = '1') OR se5) AND (sa10 OR sa12 OR se6);
    f1e <= (sa14 AND x(1) = '1') OR se1;
    f246c <= sb2 OR sb3 OR sb6;
    f3e <= se3;
    
-- Signal assignments

    y(1) <= '1' when sa14 else '0';
    y(2) <= '1' when sa2 else '0';
    y(3) <= '1' when sa3 else '0';
    y(4) <= '1' when sa4 else '0';
    y(5) <= '1' when sa5 else '0';
    y(6) <= '1' when sa6 else '0';
    y(7) <= '1' when sa7 else '0';
    y(8) <= '1' when sa8 else '0';
    y(9) <= '1' when sa9 else '0';
    y(10) <= '1' when sa10 else '0';
    y(11) <= '1' when sa11 else '0';
    y(12) <= '1' when sa12 else '0';
    y(13) <= '1' when sa13 else '0';
       
-- Next states

    NextState1 <=
       a14 when sa1 or (sa14 and x(1) = '0') else
       e1 when (sa14 and x(1) = '1') or (se1 and f246c) else
       b1 when (se1 and not f246c) or (sb1 and not f1b) else
       a13 when sb1 and f1b else
       a1;   
       
    NextState2 <=
       a2 when sb2 and f1e else
       a3 when sa2 else
       e2 when (sa3 and not f1b) or (se2 and not f1b) else
       b2;
       
    NextState3 <=
       e3 when sb3 and f1e and x(2) = '1' else
       b3;
       
    NextState4 <=
       a4 when sb4 and f3e else
       a5 when sa4 else
       e4 when (sa5 and not f1b) or (se4 and not f1b) else
       b4;
       
    NextState5 <=
       a6 when sb5 and f3e else
       a7 when sa6 and x(3) = '0' else
       e5 when (sa5 and not f1b) or (sa6 and x(3) = '1' and not f1b) or (se5 and not f1b) else
       b5;
       
    NextState6 <=
       a8 when sb6 and f1e else
       a9 when sa8 and x(4) = '1' else
       a10 when sa9 else
       a11 when (sa8 and x(4) = '0') or (sa11 and x(5) = '0') else
       a12 when sa11 and x(5) = '1' else
       e6 when (sa10 and not f1b) or (sa12 and not f1b) or (se6 and not f1b) else
       b6;
       
StateAssignmentProcess: process (CLK) is
begin
    
    if rising_edge (CLK) then
       if Reset = '1' then
         State1 <= a1;
         State2 <= b2;
         State3 <= b3;
         State4 <= b4;
         State5 <= b5;
         State6 <= b6;
       else
         State1 <= NextState1;
         State2 <= NextState2;
         State3 <= NextState3;
         State4 <= NextState4;
         State5 <= NextState5;
         State6 <= NextState6;
       end if;
    end if;
    
end process StateAssignmentProcess;

end behavioral;